Finally ready to start populating the first prototype of my new generation 48V IBC.
I'm going to do detailed solder paste metrology on all of my boards (this one included) from now on until I'm satisfied I've fixed the process issues. Not just the test vehicles.
High res imaging (Mitutoyo 5x) in progress. Let's see how it turns out. About an hour to grab the 2600 tiles.
I'm using a single focal plane roughly at the copper pad surface so the tops of the paste deposits will be blurry but I'll be able to see the outlines.
Checking the in-progress scan I see a few problem areas along the edge of the board. Maybe I bumped it with my finger tip as I took it off the jig?
Easy to rework, at least - just some passives.
Slight misalignment of the paste deposits in this area. Probably not enough to matter.
I think this is a pretty good focal plane for paste imaging. I don't need to see all the solder spheres clearly, I care about registration and approximate area of the paste deposit compared to the pad.
Ok, full scan complete and stitching. Not going to wait for the stitch to finish, it's almost 2am and I have work tomorrow but I don't want to let the paste dry on the board.
So I'm gonna stuff the board, reflow it, and get some sleep then crunch the metrology tomorrow.
For posterity and somewhat out of order: here's the reworked R5 and C7 area.
Board is reflowed, letting it cool overnight. I need to sleep.
Well, C5 has a classic head-in-pillow failure and R7 looks to have done the same, plus there's some stray solder balls around. Neither is happy.
Not seeing any other defects on initial inspection.
So the rest of the print was fine but the reworked area had issues.
Will take a more detailed look at before/after rework and see if I see any obvious root cuases.
Kid is in bed and I have more time to spend on the IBC.
Started out by reworking the two passives on the edge, then pasted the front side.
High res full-board microscope scan of the paste is running now. While I'm waiting for that, here's a few closeups of interesting areas across the board.
So now let's go back to the bottom side and try to postmortem those reflow issues I had.
First, to orient ourselves, we're looking at the underside of https://github.com/azonenberg/common-ibc/tree/main/pcb after applying solder paste but before stuffing any components.
This is a 1.14 gigapixel image stitched from 2600 image tiles acquired with a Mitutoyo 5x/0.14 objective. Focal plane is nominally at or slightly above the copper surface but the PCB isn't perfectly planar so there's some small shifts.
Zooming in at the 6 o'clock position, we can see several different defects in the solder paste:
* All of the paste deposits are displaced slightly to the northeast of nominal. The paste deposit on the north end of R8, for example, is shifted by about 155 μm. This is probably not enough to matter given the size of the pads.
* The southwest pad of C25 has almost no paste. This is probably caused by poor release from the stencil and is one of the key failure modes I hope to eliminate with electropolished stencils in the future.
*The east side of C5 and both pads of R7 look to have been smeared, probably by a finger when I was taking the board off the paste fixture (these pads are extremely close to the edge of the PCB).
After manually touching up the problematic pads, here's what they looked like under the stereo microscope.
We can see the southwest pad of C25 now has plenty of solder on it, but there are a few loose blobs of paste that I didn't get exactly in the right place.
And the solder volume on C5 and R7 looks to be quite a bit less than on the properly printed pads.
After reflow, the right side of C5 went head-in-pillow. This was the area of paste that I touched up, so I probably didn't use enough, and/or I lost some flux when I scraped the misaligned solder balls back into position.
R7 had a very similar failure, likely for the same reason.
So process optimization takeaways so far:
1) Paste release is indeed a problem on smaller apertures. I knew this, which is why I'm investigating electropolishing.
2) I need to be more careful when handling high density boards post-paste to not bump into the fresh paste deposits and smear them.
3) When reworking bad paste prints, I should put more effort into ensuring the paste/flux volume of the reworked deposit closely resembles the intended print.
I did do a full board high res image post reflow, but it didn't show any defects other than the ones I already pointed out.
There were a few loose solder balls visible near the reworked area of C25, which makes sense in retrospect.
Which brings us to the present: back side of the board had a handful of bad joints post reflow, all of which were easy to rework with an iron.
Front side has been pasted, paste quality looks excellent (nothing to rework) on initial at-a-glance inspection. High res microscope scan of front paste in progress.
Gonna go do some other stuff and come back to it in an hour. If I don't see any issues in the paste I'll start stuffing the board.
Doing all of this metrology mid-process is definitely not the fastest way to build a board but it's really nice to be able to go back to photos of what an area looked like pre reflow and root-cause a defect. So I think I'll keep doing it until I have the kinks worked out.
After losing way too much time to technical difficulties with the camera, imaging is done and the stitch is in progress.
Paste print quality is generally very good, some slight misalignments in the northeast corner but nothing that concerns me at all.
Time to start stuffing the board.
Board is in the oven cooling off, but still way too hot to touch and hand solder.
While I'm waiting let's take a look at the paste imaging results. Here's the overview (as usual, this is about a 1.2 Gpix image at full resolution)
My camera (not the PC side software, the camera itself) crashed midway through the imaging run and the white balance shifted when I rebooted it. I didn't bother to restart the whole run because I wanted to finish the board and the color shift wasn't a concern for paste metrology purposes.
Main microcontroller looks great alignment wise.
There's a small amount of flux spreading visible on the center pad (flux has expanded beyond the footprint of the solder spheres) since the board sat for a couple hours after pasting while I took a shower and did some other chores (I restarted the imaging run after an unrelated issue).
I don't think the flux flowing is that big an issue as it would happen anyway when the board heats up during reflow and the flux viscosity drops?
Top right corner showing more significant registration error. I'd call this probably 150-200um at a glance but havent done the pixel counting.
Hand soldering complete but it's too late to do any bringup tonight.
No solder issues visible during manual inspection so I an not currently planning to do a high res post solder scan of the board.
Looking back at the high res paste scan in the 9 o'clock region of the board, I do see a few print artifacts (?) on some of the LGA pads as well as the DFN to the left.
I think these will all resolve during reflow but would probably have reworked them if I had seen them earlier (it was late, lol).
Wondering if maybe my aperture size on the LGA is a little too large? I'd probably get perfectly adequate solder joint quality using less paste.
Getting ready to start bringup on the IBC and realized I forgot to put a test point on a rather important location: the 48V rail after the input protection circuit.
Luckily there's plenty of big component pads to probe at.
Hmm, that hole wasn't there before.
Seems I've got some debugging to do...
On the plus side, I don't think anything else fried. This is the input protection controller (LTC4367) which should (fingers crossed) have not enabled power to anything downstream if it wasn't happy.
But why did a part that's supposed to be nearly indestructible (its purpose is to protect downstream circuitry from out-of-tolerance inputs, ranging from -40 to +100VDC) fry when given +48?
Also, this is why I always wear safety glasses when bringing up a new board.
Thanks to my detailed design review process I make major component-frying mistakes infrequently, and even when I do there's usually just a hot and unhappy part rather than flying shrapnel.
But especially with power stuff, parts going pop is always a risk on an unproven prototype.
Here's the schematic, anyone want to give it a a second look?
Initial observations:
* Input power is on a polarized connector and verified the right way around
* Input came from a DC lab power supply with a 50ms soft start, so input dV/dt should not have been a problem
* Double checked pinout against the datasheet, looks OK
* Checked for shorts between gate and channel of Q1, none found
* VIN to ground (with the fried chip still on the board) measures 49.8 ohms. This is obviously not good, it would cause almost 1 amp to flow through whatever the fault path is.
* There is no evidence of any solder defects visible on U1.
Pulled the chip, no visible solder bridges upon removal,
But the short is gone with the chip removed.
Removed chip measures 50.8 ohms from pin 1 to pin 4. So it's internally shorted.
But why? I'll definitely decap it to have a look but that won't be right away.
Not seeing anything obviously wrong.
The LTC4367 is supposed to be functional down to +2.5V.
I'm thinking what I might do is put a second chip back on the board, give it a really low input voltage (say +5V with a 10 mA current limit or something), and measure voltages at various nodes to see if I can see anything unexpected.
With anything below +40V input, the output should be disabled, so we should not see any voltage on VOUT (and thus near zero current draw).
@azonenberg stupid question, shouldn't pin 1 of U1 be connected to vin (your schematic don't indicate that)?
